Providing design flexibility in a cache by allowing a variety of size and associativity choices, while maintaining the speed of the cache in locating/storing a requested element, may be highly advantageous for architectures that utilize a cache. However, when dealing with semiconductor technology, power savings become an evermore prevalent concern, which often leads to limiting performance or sacrificing reliability.
A typical method to save power, when dealing with cache arrays, includes running the cache arrays at lower voltages than the rest of the device, such as a processor, chipset, or other integrated circuit. Yet, lower voltages may make locations within a cache array more susceptible to soft errors, i.e. flipping of bits that result in an error. Furthermore, locations within the cache are often permanently damaged due to design, manufacture, or after manufacture event, which is often referred to as a hard error.
Traditionally, to correct hard errors, a line of cache including a hard error is replaced by a spare line. In contrast, a soft error is usually correctable by error correction code (ECC) employed by the cache array. ECC typically refers to logic that detects and may potentially locate, as well as fix errors. As an example, many cache arrays use 1-bit ECC to correct single bit errors per word or cache line.
Referring to FIG. 1, a prior art cache 100 is illustrated. Often a cache memory is simply a memory array; however, it may also be physically organized or logically viewed as having a plurality of lines/words, such as lines 106 through 113. In addition, each bit or group of bits in every line of the cache are logically viewable to form a column, such as columns, 115, 116, 117, and 118. Assuming cache 100 includes 1-bit ECC, then single errors per line, such as bit-error 130 in cache line 106, bit error 131 in cache line 109, and bit error 132 in cache line 111 may be detected and fixed.
However, as voltages to cache 100 are decreased below a critical voltage certain bits begin to fail. Therefore, to ensure reliability in cache 100 the voltage supplied to cache 100 may only be lowered to a critical voltage before lines, such as cache line 113, begin to have multiple bit errors, such as bit errors 120 and 125. As a consequence, voltage is not decreased any further to ensure reliability; however, this is at the expense of sacrificing power savings.